The field of the invention is burn-in testing of integrated circuits. In particular, the invention relates to apparatus for placing a test chip in a test fixture and cooling the chip during the test.
Standard procedure in the integrated circuit industry has been to conduct a test called a burn-in test, in which a circuit is operated at an elevated temperature and/or voltage for a period of time, while being tested for proper operation.
Operation at an elevated temperature and/or voltage stresses the circuit through the differential thermal expansion of various components and also accelerates various failure mechanisms in the transistors and interconnects that combine to make up the integrated circuit.
For example, an integrated circuit will have many thousands or millions of joints where dissimilar conductors meet. Heating and cooling cycles will put stress on these joints. The failure of any one joint through separation of the two components may cause the circuit to fail.
As technology has evolved, the operating temperatures and heat dissipation of circuits have increased. At the same time, competition has exerted pressure on manufacturers to reduce costs. Expensive methods of temperature control such as are employed in mainframe computers are not commercially practical in the field of consumer electronics or other price-sensitive markets.
Driven by industry demands to produce computer die with increasingly dense circuitry on larger die dimensions, a need for advanced means to cool the chip during the burn in operation has been revealed.
Present methods of transferring heat to and from the chip are done by means of direct contact with a chilled copper block. This method is limited by the contact area between the die and block. For the best results, it is desirable to make 100% contact between die surface and the chilled block, however, matching the surface profiles between the chilled block and die to make this a reality is not possible. There will therefore be variation in the amount of contact between one chip and another and therefore variation in thermal resistance resulting in variation of test temperature between one chip and another.
Potential damage to the die interconnect joints, test sockets and boards exist with current methods and devices used in placing and holding the block against the chip.
FIG. 3 illustrates a typical test apparatus used at present.
At the bottom of the Figure, a test table 10 supports the structure. The test system rests on table 10 on legs 22 that support board holder 20. Board holder 20 holds printed circuit board 110, which may be a production board or a special test board that holds one or more chips being tested.
Socket 115 provides a defined location for the chip and electrical contacts in conventional connections.
Substrate 117 holds the chip being tested, denoted with numeral 120, and provides a standard interface with the test board.
Electrical power and a test pattern of signals will be delivered to chip 120 through connections in substrate 117 and test board 110.
Cooling of the chip during the test is provided by a unit denoted generally by numeral 210 and having an electrical heater 220 and cooling fluid entering on flexible tube 232 and exiting on tube 234. These tubes typically carry cooling water and must be insulated from contact with the chip or with the voltage on the heating wire. An electrical ground connection 222 is provided to ensure that electrical leakage does not bias the chip itself, which is conventionally designed to operate with its outer surface at ground.
At the top of the figure, block 240 denotes a transfer mechanism, typically a hydraulic cylinder with a piston, that forces the bottom surface of heatsink 210 against the top surface of chip 120.
There is the problem of incomplete contact that will vary from chip to chip and therefore produce different operating temperatures during the test.
In addition, the application of force to improve contact carries the danger of damage to the chip.